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Tuesday, July 7, 2020 | History

3 edition of New double-byte error-correcting codes for memory systems found in the catalog.

New double-byte error-correcting codes for memory systems

New double-byte error-correcting codes for memory systems

  • 370 Want to read
  • 20 Currently reading

Published by National Aeronautics and Space Administration, National Technical Information Service, distributor in [Washington, DC, Springfield, Va .
Written in English

    Subjects:
  • Error correcting codes.,
  • Decoding.,
  • Memory (Computers),
  • Computer systems performance.,
  • Theorem proving.

  • Edition Notes

    Other titlesNew double byte error correcting codes for memory systems.
    StatementGui-Liang Feng, Xinwen Wu, T.R.N. Rao.
    Series[NASA contractor report] -- NASA-CR-201861., NASA contractor report -- NASA CR-201861.
    ContributionsWu, Xinwen., Rao, T. R. N. 1933-, United States. National Aeronautics and Space Administration.
    The Physical Object
    FormatMicroform
    Pagination1 v.
    ID Numbers
    Open LibraryOL18119040M

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New double-byte error-correcting codes for memory systems Download PDF EPUB FB2

New double-byte error-correcting codes for memory systems Article (PDF Available) in IEEE Transactions on Information Theory 44(3) - June with. Get this from a library. New double-byte error-correcting codes for memory systems. [Gui-Liang Feng; Xinwen Wu; T R N Rao; United States.

National Aeronautics and Space Administration.]. A 'read' is counted each time someone views a publication summary (such as the title, abstract, and list of authors), clicks on a figure, or views or downloads the full-text. Error control codes (ECCs) have been successfully applied to computer systems, especially to memory systems.

Learn more about Chapter 4 - Codes for High-Speed. Home Browse by Title Periodicals IBM Journal of Research and Development Vol. 28, No. 2 Error-correcting codes for semiconductor memory applications: a state-of-the-art review article Error-correcting codes for semiconductor memory applications: a state-of-the-art reviewCited by: 9.

The next two theorems give the lower bounds on check-bit length of the SEC-S e/b EL codes. Theorem Linear (N, N − R) SEC-S e/b EL codes satisfy. Proof The lower bounds on the check-bit length of the S e/b EL codes are obtained by the fact that syndromes produced by e/2 or fewer bits errors should be different from each other [WOLF63].

For odd e. Readers are presented with a full array of theoretical and practical tools to master the fine points of matrix code design strategy and technique: * Code designs are presented in relation to practical applications, such as high-speed semiconductor memories, mass memories of disks and tapes, logic circuits and systems, data entry systems, and Author: Eiji Fujiwara.

Bhaumik, J., Roy Chowdhury, D.: New Architectural Design of CA-Based Codec. IEEE Transactions on Very Large Scale Integration Systems 18(7), – () CrossRef Google ScholarCited by: 1. These codes are constructed on the basis of Hamming codes, but the decoder for these codes is smaller and can be operated at a higher speed than that of Hamming codes.

In some systems, single-byte—error-correcting (SbEC) codes or single-byte—correcting and double-byte—error-correcting (SbEC-DbEC) codes are used. This checker is sometimes required for duplication check, i.e., for comparison check. In a two-rail encoding, bits of information occur as complementary pairs: (0, 1) and (1, 0); the pair (0, 0) and (1, 1) indicate errors.

Thus, the same circuit that checks a two-rail encoding can be used to combine several self-checking checker output pairs into one : Eiji Fujiwara, Mitsuhiko Yashiro, Tsuneo Furuya.

Error-correcting codes play a fundamental role in modern communications and data-storage systems. This volume provides an accessible introduction to the basic elements of algebraic codes and discusses their use in a variety of applications. Techniques are presented for the construction of error-correcting codes for semiconductor memory subsystems that are organized in a multibit-per-chip manner.

These codes are capable of correcting all single-byte errors and detecting all double-byte errors, Cited by: 4. Abstract. A brief survey of research activities on fault-tolerant computing in Japan is presented with an emphasis on basic researches.

Industrial developments and applications in Japan will be presented elsewhere [Iharal].Author: Yoshihiro Tohma. Eiji Fujiwara. ISBN: Aug pagesAuthor: Eiji Fujiwara. On the other hand, the codes designed by parity check matrices are referred to in this book as matrix codes.

This timely book focuses on the design theory for matrix codes and their practical applications for the improvement of system reliability. As the author effectively demonstrates, matrix codes are far more flexible than polynomial codes. Samanta and J. Bhaumik, “Comments On VLSI Implementation Of Reed-Solomon Encoder Algorithm For Communication Systems” in Radioelectronics and Communications Systems Journal (Springer), vol.

57, no. 7, pp,July, (SCImago, IF). Full text of "Reliable computer systems: design and evaluation" See other formats. Memory areas with other dedication codes should be considered reserved by BIOS system. Intervals of address space, excluded from memory dedication map, are not supported by hardware.

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